Transistor transistor logic (T.sup.2 L) circuits are widely used because they offer a good trade-off between performance, power dissipation, functional density on a monolithic chip and logic flexibility. However, in the circuits high drive currents are used to drive the output transistor hard in order to obtain a fast turn on transition. The high drive currents cause excessive charge to be stored in the output transistor thereby resulting in heavy saturation of the output transistor and a consequent long turn off delay for the T.sup.2 L circuit.
A number of methods have been proposed to prevent deep saturation in the output transistor. One proposal uses a Schottky barrier diode in shunt with the base-collector junction of the transistor to clamp the voltage across the base-collector junction at a relatively low forward voltage. A disadvantage of this technique is that there is additional process complexity in making the Schottky diode when metals are used for the metallic interconnections in required cell areas, and there are some noise problems due to the fact that the characteristics of the transistor of the T.sup.2 L circuit and those of the antisaturation Schottky diode do not track each other in the manner of transistors formed on the same monolithic chip. An example of a circuit using a Schottky barrier diode in shunt with the base-collector junction of a transistor to clamp the voltage across the base-collector junction may be found in commonly assigned U.S. Pat. No. 4,069,428 filed by D. C. Reedy on Sept. 2, 1976.
A proposal which does not require the use of Schottky barrier diodes is disclosed in commonly assigned U.S. Pat. No. 3,693,032 filed by J. R. Winnard on Apr. 23, 1971 which discloses a T.sup.2 L circuit utilizing an extra emitter of the input NPN device connected to the collector of the output NPN device for saturation control, to take advantage of tracking characteristics in devices formed on the same monolithic chip.
In U.S. Pat. No. 4,021,687 filed Nov. 5, 1975 there is described a circuit for deep saturation prevention which has a PNP transistor merged with an NPN transistor to prevent saturation in the NPN transistor. As stated in this patent, a P type region serves as the base of the NPN transistor and as the emitter of the lateral PNP transistor, while an N type epitaxial layer serves as the collector of the NPN transistor and the base of the lateral PNP transistor.
An integrated injection logic (I.sup.2 L) circuit or merged transistor logic (MTL) circuit using a PNP transister merged with an NPN transistor is disclosed in IBM Technical Disclosure Bulletin Vol. 22 No. 2 July 1979 by R. Remshardt et al on pp. 617-618.
Circuits imploying double diffused PNP transistors and doped polysilicon sources and contacts for bipolar transistors are also known. U.S. Pat. Nos. 4,064,526 and 4,058,419, both filed Dec. 24, 1975, disclose a structure and a process, respectively, for a double diffused PNP transistor. In both patents the double diffused PNP emitter is formed within the base region, and a P epitaxial layer serves as a collector. Commonly assigned U.S. Pat. No. 4,110,126, filed on Aug. 31, 1977 by D. L. Bergeron et al discloses a structure where a double diffused PNP transistor is formed in an N- epitaxial layer having a P- implant serving as the PNP collector. Commonly assigned U.S. Pat. No. 4,190,466, filed on Dec. 22, 1977 by A. Bhattacharyya et al, discloses a bipolar transistor structure wherein first and second doped polysilicon layers are used as sources for the base contact and emitter, respectively, of a bipolar transistor.